1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
Recently, many electronic apparatuses incorporating NAND flash memories are commercially available. As the number of functions of these electronic apparatuses increases, it has become necessary to further increase the storage capacities of the NAND flash memories.
Unfortunately, while the distance between interconnections is shortened by the progress of micropatterning resulting from the increase in capacity, the voltage relationship between the interconnections remains unchanged from that of the preceding generation. Consequently, a leakage current in a row decoder placed near a memory cell array causes memory cell erase errors, and increases the number of defective bits.
In a data erase operation of the NAND flash memory, for example, a word line of an unselected block is set to float and boosted to an erase voltage by coupling with the well voltage (CPWELL) (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2005-191413).
In this state, a leakage current caused by a transfer transistor is generated in a block selector in a row decoder connected to the word line of the unselected block. In a memory cell of the unselected block, therefore, the electric charge of the word line boosted by coupling is removed by the leakage current, so the potential of the word line becomes lower than the erase voltage. For example, if the word line voltage drops from the erase voltage (about 20 V) to about 15 V, a potential difference of about 5 V is produced between the control electrode (CG) of the memory cell connected to the word line and the well (p-well). Since this produces a weak erased state, electrons are removed from the floating electrode (FG) of a memory cell in which data is to be held. This causes an erase error and increases the number of defective bits.
Major leakage currents caused by the transfer transistor described above during an erase operation are two leakage currents leak1 and leak2 below.
The leakage current leak1 is a leakage current between diffusion layers, which oppose each other and to which 0 V is applied, of transfer transistors in selected blocks adjacent to each other in the bit-line direction (channel-length direction).
The leakage current leak2 is a leakage current between diffusion layers, which obliquely oppose each other and to which 0 V is applied, of transfer transistors in similar selected blocks adjacent to each other in the bit-line direction.
As described above, the leakage currents leak1 and leak2 must be reduced in order to reduce erase defects.